general description the DS4412 contains two i 2 c adjustable-current dacs that are each capable of sinking or sourcing current. each output has 15 sink and 15 source settings that are pro- grammed by i 2 c interface. the full-scale range and step size of each output is determined by an external resistor that can adjust the output current over a 4:1 range. the output pins, out0 and out1, power-up in a high- impedance state. applications power-supply adjustment power-supply margining adjustable current sink or source features ? two current dacs ? full-scale current 500? to 2ma ? full-scale range for each dac determined by external resistors ? 15 settings each for sink and source modes ? i 2 c-compatible serial interface ? low cost ? small package (8-pin ?op) ? -40? to +85? temperature range ? 2.7v to 5.5v operation DS4412 dual-channel, i 2 c adjustable sink/source current dac dc-dc converter fb out sda scl out0 out1 gnd r fs0 r fs1 4.7k 4.7k v cc v cc v out0 fs0 fs1 r 0b r 0a dc-dc converter fb out v out1 r 1b r 1a DS4412 typical operating circuit ordering information rev 0; 9/07 ________________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free package. t&r = tape and reel. part temp range pin-package DS4412u+ -40c to +85c 8 sop DS4412u+t&r -40c to +85c 8 sop 1 2 3 4 8 7 6 5 v cc out1 out0 fs0 gnd fs1 scl sda sop top view + DS4412 pin configuration
DS4412 dual-channel, i 2 c adjustable sink/source current dac 2 _______________________________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +85?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, and scl relative to ground.............................................-0.5v to +6.0v voltage range on out0, out1 relative to ground ................-0.5v to (v cc + 0.5v) (not to exceed 6.0v.) operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature .....................................refer to ipc/jedec j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.7 5.5 v input logic 1 (sda, scl) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl) v il -0.3 0.3 x v cc v dc electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units supply current i cc v cc = 5.5v (note 2) 500 a input leakage (sda, scl) i il v cc = 5.5v 1 a output leakage (sda) i l 1 a v ol = 0.4v 3 output current low (sda) i ol v ol = 0.6v 6 ma r fs voltage v rfs 0.607 v output current characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units output voltage for sinking v out:sink v cc > v out:sink (note 3) 0.5 3.5 v output voltage for sourcing current v out:source (note 3) 0 v cc - 0.75 v full-scale sink output current i out:sink (note 3) 0.5 2.0 ma full-scale source output current i out:source (note 3) -2.0 -0.5 ma output-current full-scale accuracy i out:fs +25c, v cc = 4.0v; using 0.1% r fs resistor (note 4) v out0 = v out1 = 1.2v 6 % output-current temperature coefficient i out:tc (note 5) 75 ppm/c dc source +0.36 output-current variation due to power-supply change dc sink +0.12 %/v
DS4412 dual-channel, i 2 c adjustable sink/source current dac _______________________________________________________________________________________ 3 note 1: all voltages with respect to ground, currents entering the ic are specified positive and currents exiting the ic are negative. note 2: supply current specified with all outputs set to zero current setting with all inputs driven to well-defined logic levels. sda and scl are connected to v cc . excludes current through r fs resistors (i rfs ). total current includes i cc + 2.5 x (i rfs0 + i rfs0 ). note 3: the output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications. note 4: input resistors r fs must be between 2.25k and 9.0k to ensure the device meets its accuracy and linearity specifications. note 5: temperature drift excludes drift caused by external resistor. note 6: differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. the expected incremental increase is the full-scale range divided by 15. note 7: integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. the expected value is a straight line between the zero and the full-scale values proportional to the setting. note 8: timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c standard-mode timing. note 9: c b ?otal capacitance of one bus line in pf. output current characteristics (continued) (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units dc source, v out measured at 1.2v -0.02 output-current variation due to output voltage change dc sink, v out measured at 1.2v +0.12 %/v output leakage current at zero current setting i zero -1 +1 a output-current differential linearity dnl (note 6) 0.5 lsb output-current integral linearity inl (note 7) 1 lsb i 2 c ac electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units scl clock frequency f scl (note 8) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t dh:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 9) 20 + 0.1c b 300 ns sda and scl fall time t f (note 9) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 9) 400 pf
pin description name pin function sda 1 i 2 c serial data. input/output for i 2 c data. scl 2 i 2 c serial clock. input for i 2 c clock. fs1 3 fs0 5 full-scale calibration inputs. a resistor to ground on these pins determines the full-scale current for each output. fs0 controls out0, fs1 controls out1. gnd 4 ground out0 6 out1 7 current outputs. sinks or sources the current determined by the register settings and the resistance connected to fs0 and fs1. v cc 8 power supply DS4412 dual-channel, i 2 c adjustable sink/source current dac 4 _______________________________________________________________________________________ typical operating characteristics (applies to out0 and out1. v cc = 2.7v to 5.0v, sda = scl = v cc , t a = +25?, and no loads on out0, out1, fs0, or fs1, unless otherwise noted.) supply current vs. temperature DS4412 toc02 temperature ( c) supply current (ma) 80 60 40 20 0 -20 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0 -40 v cc = 5.0v v cc = 3.3v v cc = 2.7v does not include current drawn by resistors connected to fs0 and fs1. voltco (source) DS4412 toc03 v out (v) i out (ma) 4 3 2 1 2.1 2.2 2.3 2.4 2.5 2.0 05 2.2k load on fs0 and fs1 supply current vs. supply voltage DS4412 toc01 supply voltage (v) supply current (ma) 5.2 4.7 4.2 3.7 3.2 0.1 0.2 0.3 0.4 0.5 0 2.7 does not include current drawn by resistors connected to fs0 and fs1. voltco (sink) DS4412 toc04 v out (v) i out (ma) 3 2 1 -2.4 -2.3 -2.2 -2.1 -2.0 -2.5 04 2.2k load on fs0 and fs1 temperature coefficient vs. setting (source) DS4412 toc05 setting (dec) temperature coefficient ( c/ppm) 10 5 10 20 30 40 50 60 70 80 0 015 +25 c to -40 c +25 c to +85 c range for the 0.5ma to 2.0ma current-source range. temperature coefficient vs. setting (sink) DS4412 toc06 setting (dec) temperature coefficient ( c/ppm) 10 5 10 20 30 40 50 60 70 80 0 015 +25 c to -40 c +25 c to +85 c range for the 0.5ma to 2.0ma current-source range.
block diagram v cc v cc r fs0 r fs1 sda scl gnd fs0 fs1 out1 out0 current dac0 f8h f9h source or sink mode 15 positions each for sink and source mode current dac1 i 2 c-compatible serial interface DS4412 DS4412 dual-channel, i 2 c adjustable sink/source current dac _______________________________________________________________________________________ 5 typical operating characteristics (continued) (applies to out0 and out1. v cc = 2.7v to 5.0v, sda = scl = v cc , t a = +25?, and no loads on out0, out1, fs0, or fs1, unless otherwise noted.) differential linearity DS4412 toc08 setting (dec) dnl (lsb) 10 5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 015 range for the 0.5ma to 2.0ma current source and sink range integral linearity DS4412 toc07 setting (dec) inl (lsb) 10 5 -0.7500 -0.5000 -0.2500 0.0000 0.2500 0.5000 0.7500 1.0000 -1.0000 015 range for the 0.5ma to 2.0ma current source and sink range
detailed description the DS4412 contains two i 2 c adjustable-current sources that are each capable of sinking and sourcing current. each output, out0 and out1, has 15 sink and 15 source settings that are programmed through the i 2 c interface. the full-scale ranges and corresponding step sizes of the outputs are determined by external resistors, connected to pins fs0 and fs1, which can adjust the output currents over a 4:1 range. the formula to determine the positive and negative full-scale current ranges for each of the four outputs is given by: r fs = (v rfs / i fs ) x (15 / 1.974) where v rfs is the r fs voltage (see dc electrical characteristics ), and r fs is the external resistor value. on power-up, the DS4412 outputs zero current. this is done to prevent it from sinking or sourcing an incorrect current before the system host controller has had a chance to modify the device? setting. as a source for biasing instrumentation or other cir- cuits, the DS4412 provides a simple and inexpensive current source with an i 2 c interface for control. the adjustable full-scale range allows the application to get the most out of its 4-bit sink or source resolution. when used in adjustable power-supply applications (see typical operating circuit) , the DS4412 does not affect the initial power-up supply voltage because it defaults to providing zero output current on power-up. as it sources or sinks current into the feedback voltage node, it changes the amount of output voltage required by the regulator to reach its steady state operating point. using the external resistor, r fs , to set the output current range, the DS4412 provides some flexibility for adjusting the range over which the power supply can be controlled or margined. memory organization the DS4412? current sources are controlled by writing to the memory addresses in table 1. the format of each output control register is given by: where: example: r fs0 = 4.8k and register 0xf8h is written to a value of 0x8ah. calculate the output current. i fs = (0.607v / 4.8k ) x (15 / 1.974) = 949.85? the msb of the output register is 1, so the output is sourcing the value corresponding to position ah (10 dec- imal). the magnitude of the output current is equal to: 949.85? x (10 / 15) = 633.23? DS4412 dual-channel, i 2 c adjustable sink/source current dac 6 _______________________________________________________________________________________ table 1. memory addresses memory address (hexadecimal) current source 0xf8 out0 0xf9 out1 msb lsb sxxxd 3 d 2 d 1 d 0 bit name function power-on default s sign bit determines if dac sources or sinks current. for sink s = 0, for source s = 1. 0b x reserved reserved. xxx d x data 4-bit data word controlling dac output. setting 0000b outputs zero current regardless of the state of the sign bit. 0000b
sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is referenced to v il(max) and v ih(min) . start figure 1. i 2 c timing diagram i 2 c serial interface description i 2 c slave address the DS4412? slave address is 90h. i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers: master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac- tive and in their logic-high states. when the bus is idle it often initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 1 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 1 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi- cally to a normal start condition. see figure 1 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl, plus the setup and hold time requirements (figure 1). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (figure 1) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledgement (ack) or not acknowledge (nack) is always the ninth bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the ninth bit. a device performs a nack by transmitting a one during the ninth bit. timing for the ack and nack is identical to all other bit writes (figure 2). an ack is the acknowledgment that the device is prop- erly receiving data. a nack is used to terminate a DS4412 dual-channel, i 2 c adjustable sink/source current dac _______________________________________________________________________________________ 7
read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information trans- fer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write defini- tion to receive additional data bytes. the master must nack the last byte read to terminated commu- nication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately fol- lowing a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the DS4412? slave address is 90h. when the r/ w bit is 0 (such as in 90h), the master is indicating it will write data to the slave. if r/ w = 1 (91h in this case), the master is indicating it wants to read from the slave. if an incorrect slave address is written, the DS4412 assumes the master is commu- nicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to iden- tify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication writing to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and gener- ate a stop condition. remember that the master must read the slave? acknowledgement during all byte-write operations. reading from a slave: to read from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. slave address start start 1 0 0 1 0 0 0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register/memory address b7 b6 b5 b4 b3 b2 b1 b0 data stop single byte write -write resistor f9h to 00h single byte read -read resistor f8h start repeated start 90h master nack stop 1 0010000 11111 000 f8h 10010 001 1 0010000 11111 001 90h f9h stop data example i 2 c transactions typical i 2 c write transaction 00000 000 90h a) b) slave ack slave ack slave ack slave ack slave ack slave ack figure 2. i 2 c communication examples DS4412 dual-channel, i 2 c adjustable sink/source current dac 8 _______________________________________________________________________________________
DS4412 dual-channel, i 2 c adjustable sink/source current dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. application information example calculation for an adjustable power supply in this example, the typical operating circuit is used as a base to create figure 3, a 2.0v voltage supply with ?0% margin. the adjustable power supply has a dc-dc converter output voltage, v out , of 2.0v and a dc-dc converter feedback voltage, v fb , of 0.8v. to determine the relationship of r 0a and r 0b , we start with the equation: substituting v fb = 0.8v and v out = 2.0v, the relation- ship between r 0a and r 0b is determined to be: r 0a = 1.5 x r 0b i out0 is chosen to be 1ma (midrange source/sink cur- rent for the DS4412). summing the currents into the feedback node, we have the following where: and to create a 20% margin in the supply voltage, the value of v out is set to 2.4v. with these values in place, r 0b is calculated to be 267 , and r 0a is calculated to be 400 . the current dac in this configuration allows the output voltage to be moved linearly from 1.6v to 2.4v using 15 settings. this corresponds to a resolution of 25.8mv/step. v cc decoupling to achieve the best results when using the DS4412, decouple the power supply with a 0.01? or 0.1? capacitor. use a high-quality ceramic surface-mount capacitor if possible. surface-mount components mini- mize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications. i vv r ra out fb a 0 0 = ? i v r rb fb b 0 0 = iii out r b r a 00 0 = ? v r rr v fb b ab out = + 0 00 dc-dc converter fb out sda scl out0 gnd r fs0 = 4.612k 4.7k 4.7k v cc v cc v out = 2.0v fs0 r 0b = 267 r 0a = 400 v fb = 0.8v i r0a i r0b i out0 DS4412 figure 3. example application circuit package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .
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